发明名称 BUFFER MEMORY CONTROLLER
摘要 PURPOSE:To reduce data quantity in a single write-in to a buffer memory and the number of times of writ-in and to improve the utilization efficiency of the buffer memory. CONSTITUTION:This controller for a buffer memory suitable for a television telephone device and a video codeck used for a conference system consists of a variable length encoder part 2, switching circuits 3 and 4, a presence judgement circuit 6, a variable length code generation circuit 7, an escape sequence data generation circuit 8 and a stuffing code generation circuit 29. Codes with different effective data length can be incorporated in a single block designated with a prescribed bit length without extending into several data blocks, and the data width of the data block can be reduced to a minimum necessary size.
申请公布号 JPH04235437(A) 申请公布日期 1992.08.24
申请号 JP19910012852 申请日期 1991.01.09
申请人 SONY CORP 发明人 TAMURA TADASHI;EMOTO HARUICHI
分类号 G06F5/00;G06F13/38;H04L12/951;H04N5/907;H04N7/15 主分类号 G06F5/00
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