| 摘要 |
<p>PURPOSE: To synchronize an input clock signal and an output clock signal by smoothing a write address in accordance with a prescribed reference dependent upon a gap existing in input data. CONSTITUTION: The write address of an elastic storage device 103 is generated in response to an input clock signal. A smooth clock signal has a value dependent upon the duration of the gap existing in a prescribed part of an input data signal and is obtained by properly dividing the frequency of an input clock signal. The smooth clock signal controls a counter 107 to generate a smooth write address. This write address is supplied to a phase detector 102, and a controlled read address is generated in response to a new output clock signal and is supplied to the storage device 103 and a detector 102. The counter 107 stops the progress not to generate an address in the period when the gap is considered to appear, and therefore, the input clock signal is synchronized with the output clock signal.</p> |
