发明名称 Process and circuit for two-dimensional discrete cosine transformation
摘要 Device for fast parallel 2-D DCT (two-dimensional discrete cosine transformation) capable of performing a fast 2-D DCT by significantly reducing the number of multiplications while carrying out the 2-D DCT. An NxN two-dimensional input datum is rearranged into N groups in such a way as to have the same background (kernel, support) as the cosine function so as to transform a multiplication pattern (shape, form) of the cosine function (in the guise of background of a 2-D DCT) into a summation pattern. Then, the first few summations and subtractions are executed on the rearranged data. Thereby producing a first computed datum. Then, N 1-D DCTs are executed on the first few computed data. Finally, the 2-D DCT datum is produced by executing a shift procedure after having performed additions and subtractions on the 1-D DCT data in log2 N stages. <IMAGE>
申请公布号 FR2673012(A1) 申请公布日期 1992.08.21
申请号 FR19910010826 申请日期 1991.09.02
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 GYE-JONG KIM;SANG-YOOK LEE;CHO NAM-LK
分类号 G06F17/14;(IPC1-7):G06F15/332 主分类号 G06F17/14
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