CIRCUIT FOR MAKING INPUT DELAY UNIFORM AND DIGITAL SYNTHESIZER

摘要

PURPOSE: To reduce the number of flip flops necessary for equalizing input delays. CONSTITUTION: A pipeline direct digital synthesizing device supplies a series of switch blocks (each of which corresponds to each stage of an accumulator 120) to new increment data 124 and/or phase modulation data 122 to equalize input delays. Each switch block is provided with a multiplexer 131 for selecting new increment data, phase modulation data or precedently stored increment data and a flip flop 134 for storing the selected increment data. A shift register 140 supplies a selection signal 146 to each multiplexer.