发明名称 IMPROVED PATTERN MATCHING CIRCUIT
摘要 <p>PURPOSE: To detect the congruence of two data patterns at a high speed. CONSTITUTION: A pattern matcher 10 includes an error pattern generator 12, an encoder 14, adders 16-18 and a congruence detector 20 and also optionally includes a second encoder for encoding an addition value generated by the adder 18. The error pattern generator 12 compares the correspondence symbols of two 'P' symbol data patterns so as to discriminate whether the patterns are congruent or not. A symbol is bit and, therefore, the pattern is P-bit length. The error pattern generator 12 compares more than three corresponding symbols and discriminates whether or not the plural patterns are congruent, for example.</p>
申请公布号 JPH04233843(A) 申请公布日期 1992.08.21
申请号 JP19910154971 申请日期 1991.06.27
申请人 DIGITAL EQUIP CORP <DEC> 发明人 JIYON II DERUU;ROBAATO SHII FUREIMU;BAANAADO RABU
分类号 H04L7/08;G06F7/02;G06F7/60;G11B20/18;H04L7/04 主分类号 H04L7/08
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