A semiconductor wafer array comprising a plurality of wafers (10-18) of semiconductor material. Each of the wafers (10-18) is provided with cone-shaped or pyramid-shaped vias (25). Inserted in each of the vias (25) is a correspondingly shaped wad of electrically conductive compliant material for foaming continuous vertical electrical connections between the wafers (10-18) in the stack. The base of each wad makes connection to a bonding pad (32-37) on the surface (30) of a lower wafer (10-18) as well as to the electrically conductive compliant material in the lower wafer (10-18).
