| 摘要 |
<p>PURPOSE: To enable high-speed access, to simplify a circuit and to reduce the cost by providing a delay circuit, which has delay characteristics independent of an ATD pulse, at a predecoder circuit. CONSTITUTION: A capacitor C is linked between a NAND gate NA1, which applies the prescribed delay characteristics to the unit circuit of a predecoder 61, and the ground and a 1st resistor R1 is linked between the ground terminal of the NAND gate NA1 and the ground. Besides, this device is provided with a delay means for which a 2nd resistor R2 is linked between the supply voltage terminal of an inverter INT3 and a supply voltage in order to delay the output increase of the inverter INT3. Then, an inverted ATD pulse is prevented from being supplied to a NAND gate NA2 of the unit circuit. Thus, when the prescribed delay characteristics are applied, decoding is performed regardless of the ATD pulse, calling time can be accelerated and wiring between an ATD circuit and a column decoder can be removed.</p> |
