| 摘要 |
<p>A PROM compatible processor having the same size, number of pins and arrangement of pins as those of conventional PROMs, but no write-enable-signal input terminal. To write data in an input register (44), a pseudo address signal is used. Higher order two bits A14, A13 of the pseudo address signal A14-A0 represent control codes, A12-A8 thereof represent the address of the register (44), and the A7-A0 represent the data to be written. The pseudo address signal A14-A0 is given to an input/output buffer (42). The higher order two bits A14, A13 of the pseudo address signal are given to an input/output control section (41). The input/output control section (41) decodes A14, A13. When they represent the instruction of the input of the pseudo address signal, the section (41) stores the data of the A7-A0 in the storage location of the input register (44) specified by the address represented by the A12-A8. Thereby, using a read instruction, the inputting (writing) of the data is possible.</p> |
