Semiconductor memory cell.

摘要

A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors (Q1 to Q4) and having one end connected to a first node (N1), and a plurality of capacitors (C1 to C4) for data storage connected at one end to the MOS transistors (Q1 to Q4), respectively, at the end remote from the node (N1), and there is a predetermined regulation in relation of the capacitance of the capacitors. <IMAGE>