发明名称 PROCESSOR FOR WAVEFORM CONVERSION
摘要 PURPOSE:To achieve storage to memory, by ensuring waveform and digital conversion with a simple constitution, through different clock frequency for charge transfer delay (CCD) write-in and readout and A/D conversion. CONSTITUTION:A TV vertical synchronizing signal is written in the CCD element 22 by using the 1st clock alpha in the frequency <=2 the video band. This signal is read out by using the clock beta lower in the frequency than the clock alpha, and it is converted with the A/D converter 23 the timing of which is controlled with the clock beta and written in the memory 24. Further, the memory 24 is read out with the clock gamma shifted with the same frequency as the clock beta. Thus, the conversion by the converter 23 and the write-in to the memory 24 are not necessary for real time operation, and malfunction due to deficient response speed of components is not caused, and the signal is surely in digital conversion with a simple constitution, allowing the processing via the memory.
申请公布号 JPS56117396(A) 申请公布日期 1981.09.14
申请号 JP19800020087 申请日期 1980.02.20
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SATOU KENJI
分类号 H04N5/21;G01R13/20;G11C27/00;H04N5/262 主分类号 H04N5/21
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