Sigma-delta analog-to-digital converters based on switched-capacitor differentiators and delays

摘要

Sigma-delta analog to digital converters based upon switched capacitor delay and switched capacitor differentiator circuits are described. These switched capacitor circuits have the advantages that they are less sensitive to clock feed-through noise, dc offset voltage and power supply voltage, etc. Design examples of one-bit second-order sigma-delta analog digital converter are given to substantiate both design methodology, circuit features and the utility of these new circuit structures.