| 摘要 |
<p>PURPOSE:To prevent the generation of overerasure by providing erasing pulse impressing circuits and erasure verifying circuits which operate respectively independently from each other in each of bisected memory cell blocks and controlling the erasing pulse impressing circuits with the erasure verifying circuits of these blocks. CONSTITUTION:The memory cell array is bisected to memory array blocks 1a, 1b. The erasing pulse impressing circuits and erasure verifying circuits 18a and 17a, 18b and 17b which operate independently are provided in each of the blocks 1a, 1b. The circuits 18a, 18b are controlled by the respectively corresponding circuits 17a, 17b, by which the blocks 1a, 1b are erased. The erasing pulses are not impressed via the block 1b or 1a to the block 1a or 1b with which the erasing is completed in this way. The generation of the overerasing of the memory cells is thus prevented.</p> |
