| 摘要 |
<p>PURPOSE:To realize the digital variable delay circuit with less number of delay elements, less power consumption, and high resolution whose delay time is adjustable. CONSTITUTION:A differential digital input signal is fed to bases of a couple of emitter follower transistors(TRs) QP, QN and a capacitor C is connected between emitters of both the TRs. Moreover, a couple of variable current sources IP, IN to control a discharge speed of the capacitor arc connected to the emitters of both the TRs. The emitters of both the TRs are connected to an output comparator OS and a delayed digital differential output signal is outputted from the output comparator. The delay time is varied by the adjustment of the current of the variable current sources.</p> |
