发明名称 METHOD FOR PROVIDING SYNCHRONOUS OPERATION OF SEQUENCE LOGIC CIRCUIT AND DIGITAL LOGIC CIRCUIT
摘要 <p>PURPOSE: To offer a synchronous operation and also to remove the disturbance of the holding time even in the presence of clock skews when a circuit sent from a user network list is carried out. CONSTITUTION: The synchronizer flip-flops 30a and 30b are connected to the corresponding original user flip-flops at the immediately upstream side from a data path led to the flip-flops 30a and 30b. A prescribed amount of delay is added to a user original lock signal and a data signal respectively. In regard to every master clock of a user network list, a synchronizing clock signal oscillator 46 induces a synchronizer clock that is delayed compared with the user original clock. The synchronizing clock is applied to the control lead of each synchronizer flip-flop and always reaches the synchronizer clock earlier than the user clock and the user data, and also regardless of the arrival order of these user clock and data.</p>
申请公布号 JPH04227576(A) 申请公布日期 1992.08.17
申请号 JP19910112623 申请日期 1991.04.17
申请人 KUITSUKUTAAN SHISUTEMUZU INC 发明人 RODERITSUKU EI PURAISU;BAATO SHII SHIIRUGESU
分类号 H03K5/00;G06F1/10;G06F13/42;G06F17/50;H04L7/00 主分类号 H03K5/00
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