Semiconductor DRAM with read=out amplifier circuit - has driver assembly for energising first read=out amplifier sections, with MISFETs in driver assembly

摘要

The DRAM (10) cells contain each a transistor and a capacitor. The DRAM has a number of spaced cell blocks (12), each with a cell (MC) matrix of lines and columns on a substrate (14) Bil (BL) and word lines (WL) are coupled to the lines and columns respectively. PMOS and NMOS read-out amplifier sections (16, 18) are each coupled to the cell blocks. Between the PMOS sections are distributed PMOS driven FETs (20a-c) such that one FET (20b) of both sections is fitted between two adjacent PMOS sections (16a, b). The same arrangement is provided for the MMOS driver FETs (22a-c) w.r.t. the NMOS sections and the NMOS FET (22b) between the sections (18a, b). The system contains source voltage supply lines (36a, 38a). ADVANTAGE - Max. operational speed without impairing the integration density.