| 摘要 |
The arrangement for a push pull transducer comprises two capacitors (C1,C2), a series inductor (L) and a transformer (T) with matching centre tapped prim. and sec. windings. Four identical FETs are located on either side of the centre tappings of the transformer prim. (transistors T1 and T2) and (transistors T3 and T4) windings. The gate contacts of the FETs are controlled by timing signal voltages (VT1,VT2,VT3,and VT4) arranged so that VT1 = bar VT4 and VT2 = bar VT3. Gate timing signals VT1 and VT2 are synchronised so that the prim. circuit transistors never conduct simultaneously, whereas timing signals VT3 and VT4 are arranged so that the sec. circuit transistors conduct simultaneously for a short period, reducing the sec. circuit impedance and improving the overall transducer operating efficiency in comparison to single ended transducer circuits. ADVANTAGE - FET circuit uses less power and occupies smaller physical vol. than comparable bipolar transistor circuits. |
