Contact in DRAM device

摘要

In a DRAM the contacts to the source and drain of a field effect transistor comprise a metal layer (19) on a TiN layer (22) on a TiSi2 layer (22) formed on the source and drain regions (16). A low temperature oxide film (17) and a Boron Phosphor Silicate Glass (BPSG) layer (18) are formed over the gate (14) of the transistor and field oxide regions (12). The reliability of the metal wiring is thus improved, with better contact resistance, in DRAMs with high integration.