Delay test coverage enhancement for logic circuitry employing level sensitive scan design.

摘要

By selectively associating output signal lines with logic circuit input signal lines, it is possible to produce a combination logic circuit and latch string in which no pair of adjacent latches is connected to the same cone of logic in the logic circuit. This provides greatly improved capabilities for delay or AC circuit test with respect to the independence of test pairs of excitation data. The objective may also be achieved in whole or in part through the use of dummy latch elements which do not feed any logic circuit input signal lines. <IMAGE>