Word line driver circuit for dynamic random access memories.

摘要

A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the word-lines (10) to a negative potential with respect to the substrate, thereby decreasing the access time. An NMOS pull-down transistor channel (24) is implemented as a P-well within an N-well. Applying a negative potential to the source of the pull-down transistor (24) permits the transistor to be switched so that a negative potential is applied to the wordline (10) when the NMOS pull-down transistor is gated into conduction. A PMOS pull-up transistor (23) is serially connected to the NMOS pull-down transistor drain, permitting the wordline (10) to be driven positively. <IMAGE>