发明名称 SERIAL DATA COMMUNICATION APPARATUS
摘要 <p>PURPOSE: To provide a circuit for making the receiver of a communication equipment be along the bit boundary of a serially received data flow. CONSTITUTION: A circuit device delays the bit of a synchronous data flow and it is correlated to the next bit of the data flow. When the bits are equal, signals are generated and a synchronous latch is reset. Thereafter, the receiver is synchronized with input data. Thus, a general purpose synchronous/ asynchronous transmitter-receiver more highly efficient than a conventional one is obtained.</p>
申请公布号 JPH04220830(A) 申请公布日期 1992.08.11
申请号 JP19910042192 申请日期 1991.02.15
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 MAAKU ARAN JIYONSON
分类号 H04L7/00;H04L7/02 主分类号 H04L7/00
代理机构 代理人
主权项
地址