| 摘要 |
PURPOSE:To accelerate a speed and to increase a capacity by employing an FIFO controller which can simultaneously control a plurality of virtual passes. CONSTITUTION:When a memory block 2 receives a write start signal from an FIFO controller 1, the block 2 writes data for one cell in a write address. A leading word of a cell to be started by the start signal is written in a memory bank. When a read start signal from the controller 1 is received, data for one cell is output from the read address. In this case, the leading head of the cell is read from next memory bank of the final word memory bank of the cell which was previously read, and then sequentially read. The writing/reading of the respective words are deviated at the banks for the respective one words, and hence the banks to be written and read are not simultaneously conducted to be written and read, but sequentially written and read. N pieces of the banks are provided thereby to alleviate writing/reading time limits. |
