| 摘要 |
PURPOSE:To decreases, specially, the operation clock of a circuit which generates a random number digitally. CONSTITUTION:When a 1-bit shift and feedback combinational process is performed for a D-FF whose state is (a, b, c, d, e, f, g) so as to obtain a 1-bit random number, the state becomes (c+g, a, b, c, d, e, f). At this time, a feedback arithmetic circuit performs such arithmetic that the state when the 1-bit shift and feedback combinational process is performed M(=8) times in one clock cycle becomes (b+f+g, a+c+d+g, a+b+e, b+c+f, c+d+g, a+e, b+f), thereby reducing the operation clock to 1/Mth. |
