| 摘要 |
<p>PURPOSE:To improve the yield of chips by selecting all word lines at the time of writing to a memory cell before erasing and selecting the redundancy word lines substd. with the normal and defective word lines at the time of impressing an erasing pulse. CONSTITUTION:The ordinary memory cell and the memory cell connecting to the word line including defective bits are subjected to the writing before erasing by a 1st word line selecting means which is constituted of an automatic erasing circuit M1, an address counter M2, a shift register M3, a switching circuit M6, and a low decoder M7. The ordinary memory cell and the substd. spare memory cell are selected at the time of erasing by a 2nd word line selecting means which is constituted of the circuit M1, the counter M2, an address buffer M8, a predecoder M9, and the low decoder M7. Overerasing of the memory cell including the defective bits and the memory cell which is not used is prevented even if the spare is put into the low side in this way and the overerasing of the defective word lines which do not execute erasing verification is prevented.</p> |
