| 摘要 |
<p>A drive device is provided with a data latch circuit (1) which is formed of a plurality of latch means, which successively latch serial drive data and output them in parallel, and a shift register (5) having a plurality of first flip-flops (15, 17 to 20) which provide, responsive to clock pulses, latch signals for causing the latch means to latch the serial data in succession. In one aspect of the invention, the shift register also outputs an end signal (Q output of FF 21) when output of the latch signals is completed, and a gate circuit (A40) which prohibits input of the serial data to the data latch circuit (1) responsive to the end signal. In another aspect of the invention, the shift register has a second flip-flop (21) which produces an output signal (Q output of FF 21) after output of the latch signals to said plurality of latch means is completed, and a logic gate circuit (B50) receiving a latch complete signal that is output from one (FF 20) of the first flip-flops (20) upon completion of the output of the latch signals, and the output signal from the second flip-flop, and outputs a signal of the predetermined level for a predetermined period. A prohibiting circuit (14) blocks the serial data or the clock pulse responsive to an end signal output from the second flip-flop (21). <IMAGE></p> |
