发明名称 CLOCK OVERLAP ELIMINATION CIRCUIT
摘要 PURPOSE:To prevent malfunction of a logic circuit caused by overlap of a polyphase clock by using a detection signal from a detection circuit so as to correct a waveform of the polyphase clock. CONSTITUTION:A circuit 1 detecting overlap of high level of biphase clocks CLK1, CLK2 consists of inverters 3-9 and NOR gates 6,10,11. Then a detection signal outputted from the detection circuit is used to eliminate the overlapped high level of the biphase clock at a circuit 2, which consists of NAND gates 12,14 and inverters 13,15.
申请公布号 JPH04213914(A) 申请公布日期 1992.08.05
申请号 JP19900401227 申请日期 1990.12.11
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 MORI YOSHIYUKI
分类号 H03K5/151;H03K5/156 主分类号 H03K5/151
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