发明名称 Low-noise, area-efficient, high-frequency clock signal distribution line structure
摘要 An area-efficient, low-noise transmission line structure for use in integrated circuits, which may be used to carry a high-frequency AC signal from a source location to one or more destination locations. This transmission line structure effectively decouples high-frequency signals carried by a signal line from a subjacent substrate. The structure comprises a dielectric layer subjacent the entire length of the signal line, a well of semiconductor material having a conductivity type opposite to that of the substrate, with the well being positioned beneath the signal line, extending substantially the entire distance between the source location and each destination location, being electrically insulated from the signal line by the dielectric layer, and forming a P-N junction with the substrate. The junction, which is maintained in a reverse-biased state, possesses a parasitic capacitance that is larger than the parasitic capacitance existing between the signal line and the well. The reverse-biased state is maintained by application of a biasing voltage applied through ohmic contact made to one or more heavily-doped diffusion regions, which extend the length of the well and are of the same conductivity type as the well.
申请公布号 US5136357(A) 申请公布日期 1992.08.04
申请号 US19910683767 申请日期 1991.04.10
申请人 发明人
分类号 H01L23/66;H01L27/08;H03K5/15 主分类号 H01L23/66
代理机构 代理人
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