发明名称 DECODER CIRCUIT
摘要 PURPOSE:To eliminate the possibility of breakdown of insulation and to allow the high-speed driving of word lines by forming the word line driving transistors formed in N wells to a channel type and supplying the bias signals different from clock signals for writing into the N wells. CONSTITUTION:The word line driving transistors Q0, Q1... of the P channel type are formed within the N well NW1. The other bias signal phi2 is supplied without using the signal phi1 for driving word lines in order to bias the N well NW1 to a high-voltage stage. The need for increasing the gate voltage of the TRs Q0... is eliminated in this way even if the voltage of the word lines is increased in order to allow the sure writing. The load of the signal phi1 is decreased and the word line driving is speeded up.
申请公布号 JPH04212781(A) 申请公布日期 1992.08.04
申请号 JP19910021897 申请日期 1991.02.15
申请人 NEC CORP 发明人 MUROTANI KITOKU
分类号 G11C11/413;G11C11/407;G11C16/06;G11C17/00;G11C17/12;H01L21/8242;H01L27/10;H01L27/108 主分类号 G11C11/413
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