| 摘要 |
<p>PURPOSE:To relax a memory access speed being a trouble in quickening an exchange speed by providing plural memories to each of output ports and handling them as one memory logically. CONSTITUTION:Address filters 102-1-102-4 identify address information of a packet on a time division multiplex bus 106 expanded in parallel by serial parallel converters 101-1-101-4. The filters receive the packet and outputs a write request signal to buffer control sections 103-1-103-4. The received packet is latched by the control sections. The control sections send sequentially a write enable signal to FF circuits of buffer sections 104-1-104-4. The circuits receiving the enable signal send a packet to the memory, in which the packet is stored. The stored packet is outputted to output ports 105-1-105-4 in the sequence stored by a read control signal from the buffer control sections 103-1-103-4. Thus, overhead at address information processing is eliminated.</p> |
