| 摘要 |
<p>PURPOSE: To provide an architecture which makes the internal cache of a microprocessor inactive while the effective speed of the microprocessor is varied. CONSTITUTION: To control the effective speed of the microprocessor 102, a programmable timer 106 sends a pulse train and holds request pins on the microprocessor. In a pulse train cycle, the microprocessor is placed in a hold state at one logical level and operates at its ordinary maximum clock speed at the other logical level. To inactivate and restore the internal cache, the cache logic of H/W and S/W of the microprocessor is used. When the effective speed decreases, H/W control flashes the internal cache through H/W cache control to disable the cache to be used and when the microprocessor is put back to its ordinary maximum speed, the microprocessor is set automatically to an adequate state under S/W control through the cache control logic of S/W. The 'ON' state of the cache is determined by the logic and the relation between the S/W control and H/W control.</p> |
