| 摘要 |
PURPOSE:To prevent the overall length of data lines from increasing by connecting 1st I/O lines to 1st bit wire groups and 2nd I/O lines to 2nd bit line groups and extending both I/O lines in opposite directions. CONSTITUTION:A memory cell array 4 is constituted of the bit lines and word lines. The bit lines are divided into respectively a prescribed number of the 1st bit line groups and 2nd bit line groups. The I/O lines are also divided into the 1st I/O lines 10a connected to the 1st bit line groups and the 2nd I/O lines 10b connected to the 2nd bit line groups. Further, the lines 10a, 10b are respectively extended in the opposite directions from nearly the center on one side in parallel with the word lines of the array 4, i.e., toward the two long sides of a semiconductor chip 1 and are connected to an I/O line selecting circuit 6a or 6b. |
