发明名称 DEVICE FOR MAKING A SERIES OF BIT FLOW FREQUENCIES DOUBLE OR 1/2
摘要 <p>PURPOSE: To operate a device as a doubler as well as a divider. CONSTITUTION: Registers R4 to R0 are operated with a frequency F, and a register R is operated with a frequency 2F. An internal line L receives outputs from registers R4 to R0 through gates T4 to TO. Multiplexers M4 to M1 select one of the internal line, outputs of preceding registers, and the output of the register R. A multiplexer M selects the output of the register R or RO or a filling bit (r) as the output of this circuit. These gates and multiplexers are controlled.</p>
申请公布号 JPH04211509(A) 申请公布日期 1992.08.03
申请号 JP19910011661 申请日期 1991.01.09
申请人 SGS THOMSON MICROELECTRON SA 发明人 FUIRITSUPU SHIESUMARUTAN;SHIRUBEN KURITSUTE
分类号 H03J3/04;G06F5/06;H03K5/00;H03M7/00;H03M7/14;H04L7/00;H04L25/05 主分类号 H03J3/04
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