| 摘要 |
PURPOSE: To obtain gate length shorter than gate length on a mask by depositing source, drain, and gate metal by a self aligning method, and anisotropically selectively etching a GaInAs(P) layer on a semi-insulating InP substrate. CONSTITUTION: An (n) type InP channel layer 32 and a GaInAs(P) layer are grown on a semi-insulating InP substrate, and anisotropically selectively etching only the GaInAs(P) layer by using selection etching liquid so that a (111), (111) In face can be exposed. Then, when a heavily doped P-type InP layer 32 is grown for forming a (pn) composition plane, the same kind of junction type (pn) junction is operated at an etched bottom part, and a gate is formed. In this case, the actual gate length is decided according to the thickness of the GaInAs(P) layer 33 for the anisotropic selection etching, anisotropic etching angle, and gate length on a mask decided by lithography. Therefore, even when the gate length on the mask is long, short gate length can be obtained by adjusting the thickness of the GaInAs(P) layer 33.
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