| 摘要 |
PURPOSE:To miniaturize a cell and to increase a capacity by insulator-separating a p-type Si substrate, superposing an epitaxial layer, providing an accessing FET, providing a word line on a gate electrode, a capacity on an n-type layer and a second electrode layer through a capacity first electrode layer and an insulating film, connecting the bit line to other n-type layer, and extending it on an isolating layer. CONSTITUTION:An accessing FET of a DRAM is formed on a solid epitaxial layer 21 of an Si substrate 2. Part of a word line is connected to a gate electrode 5, a bit line is extended on an insulator-isolating layer 3, a polysilicon layer 18 is patterned and formed. A capacity is connected to the layer 21 and connected to one source/drain of the FET through a conductive layer 22 extended on the layer 3. With the construction, connection of the layer 7 of the FET to the bit line is eliminated, the width of the layer 7 can be reduced, the bit line 14 is disposed at a lower position than that of the capacity 16, the capacity 16 is extended above the bit line to increase the capacity. |
