| 摘要 |
PURPOSE:To obtain the pulse width modulation of a fine step without increasing the clock frequency, by using a counter having a few bits so that a variation of output mean voltage of a fine step can be obtained. CONSTITUTION:When a reference signal S1 is input to the counter circuit 21 and the clock pulse CP is counted, if a ratary detection pulse S2 is input to the latch circuit 22, the count contents at that time is held by the latch circuit 22. In this case, the low rank bit of the circuit 22 and the low rank bit count contents of the counter circuit 24, and also the high rank bit of the circuit 22 and the high rank bit count contents of the circuit 24 are compared by the ditigal comparator circuits 25a, 25b, respectively, and when both the data coincide respectively, the FF25a, 25b are reset. Also, the FF25a, 25b are set by all ''1'' of the respective high rank bit and the low rank bit of the circuit 24. As a result, the pulse width modulated waves of the respective periods can be obtained by the output terminals of the FF25a, 25b. These pulse width modulated waves are compounded and output through the resistors 26, 27, and a variation of a fine step can be obtained. |
