| 摘要 |
<p>In a structure of a memory cell including a pair of driver transistors (12, 13) of a first conductivity type and a pair of load transistors (14, 15) of a second conductivity type having active layers (62, 63) formed by semiconductor thin films, a shield electrode (72) is formed through an insulating interlayer on surfaces opposite to surfaces of the load transistors (14, 15) on a side opposite to gate electrodes (14a, 15a), and the potential of the shield electrode (72) is set such that no parasitic channels are formed in the load transistors (14, 15) at least when the memory cell does not read data, or the potential of bit lines (24, 25) formed on the surfaces of the load transistors (14, 15) on the side opposite of the gate electrodes (14a, 15a) are set such that no parasitic channels are formed in the load transistors (14, 15), thereby decreasing current consumption of a semiconductor memory device on a standby state. <IMAGE></p> |
