发明名称 PLL CIRCUIT
摘要 PURPOSE:To attain the miniaturization, non-adjustment, and low power consumption of equipment by using circuit configuration adaptive for digitization. CONSTITUTION:A composite video signal 1 is supplied to an A/D converter 2, and a first chrominance subcarrier component in the composite video signal is extracted 4 from the burst part of a digital signal. The component is sampled by the cycle of a second chrominance subcarrier, and a digital error signal is extracted 12, and it is converted 14 to an analog error signal. The high frequency component of the analog error signal is cut off by an LPF 15, and a VCO 16 is controlled by the output of the LPF 15. The output of the VCO 16 is frequency-divided 17, and frequency division output is set as the second chrominance subcarrier, and also, the output of the VCO 16 is set as the clock signal of the A/D converter 2.
申请公布号 JPH04207290(A) 申请公布日期 1992.07.29
申请号 JP19900332447 申请日期 1990.11.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRAI KIYOSHI;MORIMOTO TAKESHI
分类号 H04N9/45;H03L7/06 主分类号 H04N9/45
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