| 摘要 |
<p>A compact register circuit which can rewrite the data of a specified bit without effect to the other bits and without reading the register value by one writing operation, and can perform a bit processing rapidly. The register has a latch circuit (3) which is in connection with a data bus (2) and which, when the value of the data bus is written, takes in and holds it, and a read circuit (4) for outputting the output of the latch circuit (3) to the data bus when reading it. Further, a second read circuit (7), which feeds the output (Q) of the latch circuit (3) to the data bus even at a time other than the time when the output (Q) is read according to a predetermined control signal, is provided in this register. The value of the register is updated only when the data keeps a specified logic level at the time of writing it. <IMAGE></p> |
