| 摘要 |
In a parallel pipelined instruction processing system, one of a plurality of instruction processing units receives an input operand designated by a corresponding instruction of a given instruction block, through a corresponding input operand fetch unit from a data register block. A next address generation unit generates an address for an instruction block succeeding to the instruction block being executed. A branch address generation unit generates an address for a branch destination instruction block. When there is executed an instruction which is included in an instruction block after one machine cycle and which requires the next address supplied from the next address generation unit as an input operand the one instruction processing unit receives the next address directly from a short path control unit. In this case, the reading of the instruction block and the generation of the next address are concurrently executed, and the reading of the input operand and the generation of the branch address are concurrently executed. <IMAGE> |
