| 摘要 |
PURPOSE:To prevent deviation in the convergence due to an offset principally without production of a temperature drift by employing a sample-and-hold circuit having a time interval between charging and discharging operations. CONSTITUTION:Charging is implemented in a timing of a clock signal CK2 and discharging is implemented in a timing of a clock signal CK3 by using a capacitor C1 and a sample-and-hold circuit 5 samples and holds a charge/ discharge signal waveform inputted in a timing of a clock signal CK4. A sampled and held voltage is inputted to a comparator circuit 3 and the result of comparison with a reference voltage Vref is stored in a capacitor C3 mounted externally to the IC, a charge/discharge current source Icont is controlled by the output of the result of comparison and a negative feedback loop is formed entirely so that the sample-and-hold output is equal to the reference voltage Vref. Thus, no temperature drift takes place and the deviation in the convergence time constant due to offset is prevented principally. |
