| 摘要 |
<p>PURPOSE:To eliminate dispersion in a delay time till the transmission of a packet after the end of packet composition and to attain packet composition of plural time slots by using an address control circuit so as to execute the packet composition sequence. CONSTITUTION:A packet composition memory 101 stores information for one or plural time slots. Then a write address control section 102 and a read address control signal 103 use a memory access control circuit 105 to access a packet composition memory 101 alternately and implement write/read at a same speed, and a speed conversion circuit 106 stores sequentially a read output of the packet composition memory 101 and reads the output signal at a high speed in a burst way when one packet is stored. Thus, dispersion in a delay time till the packet is sent after the end of composition of the packet is eliminated and the packet of plural time slots is composed.</p> |
