| 摘要 |
An X-Y addressable imager utilizes a gate connection of a source-follower-connected MOSFET to isolate inherent capacitance of each horizontal signal line of the imager from a vertical signal line that couples the MOSFETs to a common output circuit, including a load resistor for the source followers. In one embodiment the horizontal signal lines are assigned to different groups, and each group is coupled through a different one of plural vertical signal lines to the common output circuit. At least one multiplexer couples one vertical signal line at a time to the common output circuit. Also shown is imager array scanning logic for effecting variable integration of array pixels.
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