发明名称 OUTPUT PORT FOR CPU
摘要 <p>PURPOSE:To reduce the lead of a software in a write processing by connecting the D flip-flop of the output port of a CPU to one part of the address port for memory of a random access memory. CONSTITUTION:A D flip-flop 33 of an output port 3 is connected to one part of an address decoder 21 for memory of a random access memory 2. When a CPU 1 writes data to be transferred to the outside in the address of the address decoder 21 for memory shared by the D flip-flop 33 and the random access memory 2, write to the output port 3 and the random access memory 2 can be simultaneously executed. Thus, when the transfer of data to the outside and the processing of further using the data are frequently executed, the load of the software is reduced.</p>
申请公布号 JPH04205282(A) 申请公布日期 1992.07.27
申请号 JP19900333670 申请日期 1990.11.30
申请人 FUJITSU TEN LTD 发明人 YAMADA NORIO
分类号 G06F15/78 主分类号 G06F15/78
代理机构 代理人
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