发明名称 NOVEL TRANSACTION SYSTEM ARCHITECTURE
摘要 <p>A novel transaction system (400) is provided which includes a CPU (387) and a plurality of peripherals (391-1 through 391-7). Communication between the CPU and peripherals is via a local area network, a communication port or a high speed serial bus (350) by which each peripheral is connected in common to the CPU. The CPU is also connected to various memory devices via a parallel bus which provides a higher bandwidth than the high speed serial bus. The CPU is also aware of time delays associated with operations performed by various peripheral devices and can send data to the plurality in a multiplexed fashion, thereby increasing system speed as a CPU is utilizing valuable time which would otherwise be spent waiting for a given peripheral to process an initial piece of data.</p>
申请公布号 WO1992012486(A1) 申请公布日期 1992.07.23
申请号 US1992000140 申请日期 1992.01.09
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