PLL using asynchronously resettable divider to reduce lock time

摘要

An asynchronously resettable counter/divider (25) in a phase-locked loop (PLL) for a frequency synthesizer (12) reduces the lock-up time for the PLL by resetting the resettable counter/divider when the phase difference between the output signal from a VCO (20, 21) and a low frequency reference signal (30) exceeds a predetermined value.