发明名称 |
Erasure of eeprom memory arrays to prevent over-erased cells |
摘要 |
The device and process of this invention provide for eliminating reading errors caused by over-erased cells by subsequently applying alternating erasing and programming pulses to the cells of an EEPROM array, starting with relatively high-energy-level erasing and programming voltages, decreasing the energy-level of each of the alternating erasing and programming voltages. The initial, relatively high-energy-level pulses should have sufficient energy to cause all of the cells to be programmed and to cause all of the cells to be over-erased. The energy-levels are decreased until electron transfer between floating gate and a source or drain region ceases. As the energy-levels are decreased, the threshold voltage range of the memory cells is compacted. The final threshold voltages are distributed within a preselected narrow range of positive values that are less than a predetermined wordline select voltage.
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申请公布号 |
US5132935(A) |
申请公布日期 |
1992.07.21 |
申请号 |
US19900509532 |
申请日期 |
1990.04.16 |
申请人 |
ASHMORE, JR., BENJAMIN H. |
发明人 |
ASHMORE, JR., BENJAMIN H. |
分类号 |
G11C16/10;G11C16/14;G11C16/34 |
主分类号 |
G11C16/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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