| 摘要 |
PURPOSE:To execute synchronization with a little delay by providing a signal synchronous circuit which controls the change timing of a signal by means of a phase relation and synchronizes the signal with the clock of the other digital synchronous circuit without causing a metastable state. CONSTITUTION:When the signals are transferred between the two digital synchronous circuits 11 and 12 which use respectively different frequency clocks, the signal which is from one digital synchronous circuit and which is not synchronized with the clock of the other digital synchronous circuit is synchronized with the clock of the other digital synchronous circuit by the signal synchronous circuit 16. In this case, the phase relation between the two clocks used by the two digital synchronous circuits 11 and 12 is adjusted through the use of a PLL(Phase Locked Loop) principle, and the signal is synchronized with the clock of the other digital synchronous circuit by the phase relation without causing the metastable state. Thus, delay time for synchronizing is shortened without causing the metastable state. |
