SYSTEM FOR CONTROLLING RESETTING OF MEMORY

摘要

PURPOSE:To prevent the content of a DRAM from being destroyed when a reset signal is inputted by logically disconnecting an access device section from DRAM access when the reset signal is asynchronously inputted to the access device section and the access device section is forcibly terminated. CONSTITUTION:An access device section 2 is connected with a DRAM access controller section 3 through a common bus 6 and the section 3 is connected with a DRAM section 4 through a bus 5. In case the DRAM access strobe line from the section 2 and DRAM address strobe line from the section 3 are turned on when a reset signal is inputted, the DRAM access strobe line is logically disconnected from the section 3 and the normal cycle is executed by using the DRAM address strobe line only. Therefore, the content of a DRAM can be prevented from being destroyed when a reset signal is inputted.