发明名称 PEAK LEVEL DISCRIMINATOR
摘要 PURPOSE:To detect a peak level of an input signal without a time delay when it is lower than a specified value by comparing a deviation signal between a reference signal and the input signal with a low level reference signal. CONSTITUTION:A reference signal generating circuit 5 generates a reference signal 1a synchronously with an input signal 3a and of the same waveform and a prescribed constant level. The input signal 3a and the reference signal 1a are subtracted by a subtractor circuit 6 and a deviation signal 1b of a peak level is inputted to an absolute value amplifier circuit 1, from which an absolute value signal 1c is obtained. The absolute value signal 1c is compared with a low level reference signal 3c outputted from a low level reference signal generating circuit 2 at a voltage comparator 3 and when the absolute value signal 1c exceeds the low level reference signal 3c, the polarity of the low level detection section 1d being an output of the voltage comparator 3 is inverted. Thus, it is not required to provide a margin time for level discrimination and the level decrease in an input signal is detected at a high speed.
申请公布号 JPH04196616(A) 申请公布日期 1992.07.16
申请号 JP19900321896 申请日期 1990.11.26
申请人 MITSUBISHI ELECTRIC CORP 发明人 KOURA MAKOTO;HIRANO KOJIRO
分类号 H03K5/1532;H03K5/153;H03K12/00 主分类号 H03K5/1532
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