发明名称 Memory access control for microcomputer - using buffer that operates with fast or slow system memory
摘要 A microprocessor system has a buffer memory used for handling instrutions that can be associated with a fast or slow memory. When the instruction code is not in the buffer the central unit determines if the memory to be accessed is fast or slow. If fast a direct access is instructed. The buffer stage has parallel elements (2a, 2b) and transistor (2c, 2d) inputs. Signal inputs (1a, 1d) control the state of the buffer, such that the data can circulate or be transmitted. ADVANTAGE - Improved reliability and timing control of system.
申请公布号 DE4200285(A1) 申请公布日期 1992.07.16
申请号 DE19924200285 申请日期 1992.01.08
申请人 MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP 发明人 UMEKI, TSUNENORI;INOUE, HIROHIKO, ITAMI, HYOGO, JP
分类号 G06F9/32;G06F9/38;G06F12/00;G06F12/02;G06F12/06 主分类号 G06F9/32
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