| 摘要 |
<p>PURPOSE:To eliminate a feedback loop and to suppress the generation of jitter caused by the instability of a loop characteristic by realizing a byte/bit conversion part to enable conversion to a bit stuff signal without using any digital PLL circuit in the jitter suppressing circuit for the clock of a synchronizing transmission network. CONSTITUTION:This jitter suppressing circuit is composed of a write clock generation part 1 to generate the clock corresponding to only the main signal of a received data, buffer memory 2 to store the data of the main signal according to the clock from the write clock generation part 1, byte/bit conversion part, bit stuff part 4 to generate the read clock of the buffer memory 2, and smoothing part 5 to generate the asynchronous transmission network data by smoothing the missed clocks at overhead byte positions. The byte/bit conversion part 3 accumulates the number of bits in a stuff operation by an accumulation part 3a based on the byte stuff signal and equally distributes the accumulated value by a distributor 3b so as to generate the bit stuff signal smoothed by moving average within fixed time.</p> |
